Method for thin film resistor integration in dual damascene structure

ABSTRACT

A thin film resistor ( 55 ) is formed over an etch stop layer  40 . Contact pads ( 65 ) are formed n the thin film resistor ( 55 ) and a dielectric layer ( 80 ) is formed over the thin film resistor ( 55 ). Metal structures ( 120  are formed above the thin film resistor ( 55 ) and metal ( 110 ) is used to fill a trench and via formed in the dielectric layer ( 80 ).

FIELD OF THE INVENTION

The invention is generally related to the field of thin film resistorsand more specifically to a method of forming a thin film resistor in adual damascene structure with copper interconnects.

BACKGROUND OF THE INVENTION

Thin film resistors are very attractive components for high precisionanalog and mixed signal applications. In addition to a low thermalcoefficient of resistance, low voltage coefficient of resistance, andgood resistor matching they should provide good stability under stress.

High frequency mixed signal applications require the use of copperinterconnects. Integrated circuit copper interconnects are formed usingdamascene processes. In a damascene process a trench is first formed ina dielectric layer. The trench is then filled with copper and the excesscopper is removed by a number of methods including chemical mechanicalpolishing.

The formation of thin film resistors in an integrated circuit containingcopper interconnects presents many challenges. The thin film resistor isnot formed using copper and so is incompatible with existing damasceneprocesses. The incompatibility is exacerbated by the requirement thatthe thin film resistors be formed in the same levels as the copperinterconnects. There is therefore a need for a method to form thin filmresistors in integrated circuits with copper interconnects formed usingdamascene processes.

SUMMARY OF THE INVENTION

The instant invention describes a method for integrating a thin filmresistor into an integrated circuit comprising copper interconnectsformed using dual damascene structures. In an embodiment of the instantinvention an etch stop layer is formed on a dielectric layer. A thinfilm resistor is formed over the etch stop layer and contact pads areformed on the thin film resistor. A second dielectric layer is formedover the thin film resistor and at least one trench is formed in thesecond dielectric layer. At the same time thin film resistor vias areformed above the contact pads on the thin film resistor. A via trench isformed in the trench structure and metal is formed in the trench, viatrench, and thin film resistor vias.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1(a) to FIG. 1(f) are cross-section drawings illustrating anembodiment of the instant invention.

FIG. 2(a) to FIG. 2(d) are cross-sectional drawings illustrating afurther embodiment of the instant invention.

Common reference numerals are used throughout the figures to representlike or similar features. The figures are not drawn to scale and aremerely provided for illustrative purposes.

DETAILED DESCRIPTION OF THE INVENTION

While the following description of the instant invention revolves aroundFIGS. 1-2, the instant invention can be utilized in many semiconductordevice structures. The methodology of the instant invention provides asolution to forming thin film resistors in integrated circuitscomprising copper interconnects.

An embodiment of the instant invention is shown in FIG. 1(a)-FIG. 1(f).As shown in FIG. 1(a) a metal interconnect 20 is formed over adielectric layer 10. The dielectric layer 10 is formed over asemiconductor substrate and any number of intervening layers. Thesemiconductor and any intervening layers have been omitted from theFigures for clarity. Although omitted from the Figures, the layersbeneath the dielectric layer 10 will comprise any number of activedevices including MOS and/or bipolar transistors as well as any numberof metal interconnect levels. As shown in FIG. 1(a) an inter-leveldielectric layer 30 is formed over the metal interconnect layer 20. Theinter-level dielectric layer 30 can comprise silicon oxide formed usingany suitable method including chemical vapor deposition. In a firstembodiment the inter-level dielectric layer 30 is formed using materialselected from the group comprising TEOS silicon oxides, PECVD siliconoxides, silicon nitrides, silicon oxynitrides, silicon carbides, spin-onglass (SOG) such as silsesquioxanes and siloxane, xerogels or any othersuitable material. Following the formation of the inter-level dielectriclayer 30, an etch stop layer 40 is formed over the inter-leveldielectric layer 30. In an embodiment the etch stop layer 40 cancomprise silicon nitride, silicon carbide, silicon oxynitride,combinations of one or all of these and other suitable layers, and anyother suitable dielectric material. A thin film resistor layer 50 isthen formed over the etch stop layer 40. In subsequent processing theresistor layer 50 will be etched to form the thin film resistor (TFR).In an embodiment of the instant invention the resistor layer 50 isformed using a silicon chromium (SiCr) alloy, nickel chromium (NiCr)alloy, tantalum nitride, titanium nitride, tungsten, or any othersuitable material. A photoresist layer 58 is formed and patterned overthe thin film resistor layer 50 and will be used to define the TFRduring the etching process.

Shown in FIG. 1(b) is the TFR 55 formed by etching the resistor layer 50using the photoresist layer 58 shown in FIG. 1(a) as a masking layer.The resistor layer 50 can be etched using any suitable dry or wetetching process. Following the formation of the TFR structure 55 aconductive contact layer 60 is formed over the TFR structure 55. In anembodiment the conductive contact layer 60 is formed using titaniumnitride, titanium tungsten, or any other suitable conductive material.In further embodiments of the instant invention the conductive contactlayer 60 can comprise multiple layers formed using layers comprised ofthe same or differing conductive material. Following the formation ofthe contact layer 60, patterned photoresist 70 is formed over thecapping layer as shown in FIG. 1(b) and will be used to pattern thecontact layer 60.

Following the etching of the contact layer 60 shown in FIG. 1(b),contact pads 65 are formed as shown in FIG. 1(c). The contact pads 65will protect the TFR 55 during the subsequent trench etch etch.Following the formation of the contact pads 65, an inter-leveldielectric layer 80 is formed over the TFR 55. The inter-leveldielectric layer 80 can comprise silicon oxide formed using any suitablemethod including chemical vapor deposition. In an embodiment theinter-level dielectric layer 80 is formed using material selected fromthe group comprising TEOS silicon oxides, PECVD silicon oxides, siliconnitrides, silicon oxynitrides, silicon carbides, spin-on glass (SOG)such as silsesquioxanes and siloxane, xerogels or any other suitablematerial. Following the formation of the inter-level dielectric layer80, patterned photoresist layers 90 are formed on the inter-leveldielectric layer 80. The patterned photoresist layers 90 will functionas etch masks during the subsequent etching of vias and trenches in thedielectric layer 80.

Shown in FIG. 1(d) is the structure of FIG. 1(c) following thesimultaneous etching of TFR vias 92 and a trench 94 in the inter-leveldielectric layer 80. Although only a single TFR and trench is shown inthe Figure, it should be noted that the method of the instant inventioncould be used to form any number of trench and via structures in thedielectric layer in addition to the TFR vias. It should also be notedthat a via will be used in the instant invention to describe a structurethat contacts an underlying conductive layer such as a TFR, a metalinterconnect, or an electronic device. A trench will be used to describethe structure formed in the dielectric layer in which a metalinterconnect line will be formed. The etching of the inter-leveldielectric layer 80 in FIG. 1(d) is performed using a dry etch processthat is designed to stop on the etch stop layer 40. In the case of asilicon oxide dielectric layer 80 and a silicon nitride etch stop layer40, any dry etch process with high silicon oxide to silicon nitrideselectivity can be used. It should be noted that during the etching ofthe dielectric layer 80, the contact pads 65 will protect the regions ofthe TFR 55 that would have been exposed to the etch process. The etchprocess used should therefore also have high selectivity between thedielectric layer 80 and the contact pads 65. The etched TFR vias 92 willbe used to provide electrical contact to the TFR 55 and a copperinterconnect metal line will be formed in the trench structure 94.

Following the formation of the trench 94 and TFR vias 92 shown in FIG.1(d), a patterned photoresist layer 100 is formed and used as a maskduring the formation of the trench via 96. The trench via 96 is formedby etching through the etch stop layer 40 and the underlying dielectriclayer 30. As shown in FIG. 1(f), following the formation of the trenchvia 96, the photoresist layer 100 is removed and metal 120 and 110 isformed in the TFR vias and the trench and trench via respectively. In anembodiment of the instant invention the metal formed can comprise copperor any other suitable metal. For copper metal, 120 and 110 can be formedusing any known integrated circuit processing method including coppermetal deposition and chemical mechanical polishing. Following theformation of the structure shown in FIG. 1(f), the integrated circuitcan be completed using known manufacturing methods.

A further embodiment of the instant invention is shown in FIG. 2(a)-FIG.2(d). Shown in FIG. 2(a) is a metal interconnect 20 is formed over adielectric layer 10. An inter-level dielectric layer 30 is formed on themetal interconnect layer 10. The inter-level dielectric layer 30 cancomprise silicon oxide formed using any suitable method includingchemical vapor deposition. In a first embodiment the inter-leveldielectric layer 30 is formed using material selected from the groupcomprising TEOS silicon oxides, PECVD silicon oxides, silicon nitrides,silicon oxynitrides, silicon carbides, spin-on glass (SOC) such assilsesquioxanes and siloxane, xerogels or any other suitable material.Following the formation of the inter-level dielectric layer 30, a thinfilm resistor 55 and contact pads 65 are formed as described above. Inan embodiment of the instant invention the resistor layer is formedusing a silicon chromium (SiCr) alloy, nickel chromium (NiCr) alloy,tantalum nitride, titanium nitride, tungsten, or any other suitablematerial.

Following the formation of the TFR 55 and the contact pads 65, aninter-level dielectric layer 80 is formed over the TFR 55. Theinter-level dielectric layer 80 can comprise silicon oxide formed usingany suitable method including chemical vapor deposition. In anembodiment the inter-level dielectric layer 80 is formed using materialselected from the group comprising TEOS silicon oxides, PECVD siliconoxides, silicon nitrides, silicon oxynitrides, silicon carbides, spin-onglass (SOG) such as silsesquioxanes and siloxane, xerogels or any othersuitable material. Following the formation of the inter-level dielectriclayer 80, patterned photoresist layers 90 are formed on the dielectriclayer 80. The patterned photoresist layers 90 will function as etchmasks during the subsequent etching of trenches in the dielectric layer80.

Shown in FIG. 2(b) is the structure of FIG. 2(a) following thesimultaneous etching of TFR vias 92 and the trench 94 in the dielectriclayer 80. The etching of the inter-level dielectric layer 80 in FIG.2(b) is performed using a timed dry etch process that is designed tostop upon etching through the dielectric layer 80. It is not criticalthat the etch process stop immediately at the interface between thedielectric layers 80 and 30. It is however important that the contactpads 65 be exposed following the etch process. During the etching of theinter-level dielectric layer 80, the contact pads 65 will protect theregions of the TFR 55 that would have been exposed to the etch process.This implies that the etch process used should also have highselectivity between the dielectric layer 80 and the contact pads 65. Theetched TFR vias 92 will be used to provide electrical contact to the TFR55 and a copper interconnect will be formed in the trench structure 94.

Following the formation of the trench 94 and TFR vias 92 shown in FIG.2(b), a patterned photoresist layer 100 is formed and used as a maskduring the formation of the trench via 96. The trench via 96 is formedby etching through the etch stop layer 40 and the underlying inter-leveldielectric layer 30. As shown in FIG. 2(d), following the formation ofthe trench via 96, the photoresist layer 100 is removed and copper metal120 and 110 is formed in the TFR vias, the trench, and the trench via.The copper metal 120 and 110 can be formed using any known integratedcircuit processing method including copper metal deposition and chemicalmechanical polishing. Following the formation of the structure shown inFIG. 2(d), the integrated circuit can be completed using knownmanufacturing methods.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the inventionwill be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

We claim:
 1. A method for forming a integrated circuit thin filmresistor, comprising: forming a first dielectric layer over asemiconductor; forming an etch stop layer over said dielectric layer;forming a thin film resistor on said etch stop layer; forming a seconddielectric layer over said thin film resistor; simultaneously forming atleast one trench and thin film resistor vias in said second dielectriclayer; forming a trench via in said at least one trench; and fillingsaid thin film resistor vias, said trench and said trench via with ametal.
 2. The method of claim 1 wherein said second dielectric layercomprises a material selected from the group consisting of TEOS siliconoxides, PECVD silicon oxides, silsesquioxanes, siloxane, and xerogels.3. The method of claim 2 wherein said etch stop layer comprises siliconnitride.
 4. The method of claim 1 further comprising forming contactpads on said thin film resistor wherein said thin film resistor vias arepositioned above said contact pads.
 5. The method of claim 1 whereinsaid thin film resistor is formed using a material selected from thegroup consisting of silicon chromium (SiCr) alloy, nickel chromium(NiCr) alloy, tantalum nitride, titanium nitride, and tungsten.
 6. Amethod for forming a thin film resistor, comprising: forming a firstdielectric layer over a semiconductor; forming a thin film resistor oversaid first dielectric layer; forming a second dielectric layer over saidthin film resistor; simultaneously forming at least one trench and thinfilm resistor vias in said second dielectric layer; forming a trench viain said at least one trench; and filling said thin film resistor vias,said trench and said trench via with a metal.
 7. The method of claim 6wherein said second dielectric layer comprises a material selected fromthe group consisting of TEOS silicon oxides, PECVD silicon oxides,silsesquioxanes, siloxane, and xerogels.
 8. The method of claim 6further comprising forming contact pads on said thin film resistorwherein said thin film resistor vias are positioned above said contactpads.
 9. The method of claim 6 wherein said thin film resistor is formedusing a material selected from the group consisting of silicon chromium(SiCr) alloy, nickel chromium (NiCr) alloy, tantalum nitride, titaniumnitride, and tungsten.
 10. An integration method for forming aintegrated circuit thin film resistor, comprising: forming a firstdielectric layer over a semiconductor; forming an etch stop layer oversaid dielectric layer; forming a thin film resistor on said etch stoplayer; forming contact pads on said thin film resistor; forming a seconddielectric layer over said thin film resistor and said contact pads;simultaneously forming at least one trench and thin film resistor viasin said second dielectric layer wherein said thin film resistor vias arepositioned above said contact pads; forming a trench via in said atleast one trench; and filling said thin film resistor vias, said trenchand said trench via with a metal.
 11. The method of claim 10 whereinsaid second dielectric layer comprises a material selected from thegroup consisting of TEOS silicon oxides, PECVD silicon oxides,silsesquioxanes, siloxane, and xerogels.
 12. The method of claim 10wherein said etch stop layer comprises silicon nitride.
 13. The methodof claim 1 wherein said thin film resistor is formed using a materialselected from the group consisting of silicon chromium (SiCr) alloy,nickel chromium (NiCr) alloy, tantalum nitride, titanium nitride, andtungsten.